1. Technical Field
The present invention relates in general to a system and method for efficiently and accurately measuring the noise susceptibility of an integrated circuit design, and in particular to a system and method which can analyze multiple circuit topologies for potential noise failure problems. Still more particularly, the present invention relates to an integrated circuit noise measuring and noise analysis system for determining the maximum noise which might be induced into a susceptible circuit.
2. Description of the Related Art
Avoiding problems created by noise through noise analysis is a critical step in sub-micron integrated circuit design. Ever increasing requirements for integrated circuit performance have led to widespread utilization of dynamic logic circuit families and derivatives of dynamic logic families in integrated circuits. Dynamic logic families are aggressive circuit families, which trade noise margin for timing performance. Therefore, dynamic logic families are more susceptible to noise failure than conventional static logic. There is an ever increasing need for noise analysis methods and systems to analyze high speed integrated circuits.
Currently three basic methods: circuit simulation; timing simulation; and, model order reduction are prevalent in noise analysis. However, these techniques are inefficient for analyzing the massive amount of interconnect data which are present in state-of-the-art integrated circuits. Efficient techniques for accurate estimation of coupled noise in on-chip interconnects are presently a topic of intense investigation.
Timing analysis and power analysis have always been critical in the integrated circuit design process. With increasing operating frequencies, noise analysis and interference prevention are becoming more important in the integrated circuit design process. In many cases, interference prevention is more important than timing and power analysis. Advances in process technology have allowed a substantial reduction in the minimum distance between adjacent wires in an integrated circuit. Closer proximity of wires in an integrated circuit increases the coupling capacitance between a wire or circuit device and adjacent wires or devices.
Integrated circuit design constraints dictate that the distance between two wires in an integrated circuit can be reduced more than the height of the wire. Thus, the height of a wire on an integrated circuit is typically greater than the width of the wire. The aspect ratio of each wire and corresponding parallel surface area between two wires causes an increase in the ratio of coupling capacitance to ground plane capacitance.
For present day integrated circuits, the ratio of coupling capacitance to ground plane capacitance can be as high as thirty five percent. As a result of the increase in the coupling capacitance, a transient voltage or current on a wire, a node, or a net can adversely affect neighboring signals. If a circuit or net is quiet and that circuit's neighbor is active, capacitive coupling can induce a noise pulse in the quiet circuit. This coupling phenomena can have a detrimental effect on circuit response. For example, a coupled noise pulse can erroneously switch the state of a transistor which is required to be in a different state. Undesired switching of a single transistor can "lock up" an entire computer system rendering the computer system unresponsive to all input.
Over the last several years, dynamic logic circuit families and their derivatives have gained wide-spread acceptance. Dynamic circuits utilize a clock signal, or clock-like signal, to pre-charge an output driver. The advantage of dynamic logic is that the capacitive load of the output driver is substantially reduced as compared to prior topologies. Therefore, the core logic stage which drives the output stage can operate at faster speeds and the chip can provide reliable data to other parts of the computer system at higher clock speeds.
Complementary metal oxide semiconductor (CMOS) output driver structures utilize P-type transistors to pull logic signals up and N-type transistors to pull logic signals down. Hence, the term Complementary-MOS. Dynamic logic circuits utilizes only a single N-MOS pull down transistor for an output driver. In dynamic logic families the output stage loads the core logic with only the capacitance of a single N-MOS transistor. In prior CMOS circuits the input capacitance of an output stage is comprised of both a N-MOS transistor and a P-MOS transistor. Consequently, CMOS core logic is loaded with over twice the capacitance of the core logic of dynamic logic circuits. The switching voltage of a transistor in a dynamic logic gate is the threshold voltage of a single N-MOS transistor. In conventional CMOS circuits the switching voltage is half of the supply voltage. Today's manufacturing techniques allow the threshold voltage of a transistor to be close to zero.
In summary, CMOS circuits are slower because they require a higher voltage to switch logic states and signal rise times are slowed by the higher input capacitance. Hence, dynamic logic circuits trade noise margin, or susceptibility to noise, for faster switching, reduced circuit delay and ultimately, faster operating speed.
Presently, greater utilization of noise analysis in the design phase of integrated circuits is required due to the reduced noise margin and increased noise susceptibility. When an integrated circuit is in the design phase, the emphasis of noise failure analysis can be more urgent than the problem of timing failure analysis. For most circuits, timing failure can be recovered by changing the clock speed to allow more time for a signal to propagate. However, noise is caused by many uncontrollable variables such as capacitive coupling and input slope. These variables are much more difficult to control after an integrated circuit is in production. For example, changing the capacitive coupling within an integrated circuit, generally, requires rewiring the integrated circuit to change the location of wires on the chip. If a noise problem goes undetected to the fabrication stage, correcting the noise problem will require an expensive second fabrication run.
Various transient analysis techniques can be utilized to estimate noise interference. Circuit or timing simulation techniques, such as SPICE, can be utilized to calculate noise levels. Modelling electrical characteristics such as coupling capacitance yields acceptable answers if a designer has adequate computational power, available time to detail the input, and additional time to wait for a solution. Circuit simulation methods are no longer sufficient to analyze noise, particularly in dynamic logic families.
A linear circuit model provides an accurate estimation for most coupled noise problems. To create a linear model, specialized linear model reduction techniques are utilized. Transient analysis in dynamic logic families through numerical integration or moment matching methods require considerable computational complexity and unacceptably long computation time. Model reduction requires repeated matrix factorizations, solutions to eigenvalues and solutions to time exponential evaluations. Generally, model order reduction yields a complete transient response of noise waveforms, but the computational cost of model order reduction is overburdening. Model reduction reduces the computational cost compared to complete numerical integration, but given the enormous complexity of today's interconnects, the required computation time is still unacceptable to most integrated circuit designers.
Utilizing modern moment matching methods can require more than a day to determine noise levels in a modern microprocessor circuit. The inefficiencies are even greater if noise analysis is to be utilized within layout design systems which calculate placement and routing.
Currently, most layout design systems utilize a geometric model for noise analysis. Geometric model systems are based on geometric distance between two wires. However, these simple formulas are not based upon theoretical electrical principles and hence, do not provide the required accuracy. Geometric models calculate interference merely from spatial arrangements.
Currently noise analysis and noise avoidance techniques are either inaccurate or inefficient, especially for dynamic logic families. Accurate moment matching methods or circuit simulation techniques are inefficient for both noise verification and noise avoidance. Hence, a more efficient electrical measurement system for noise analysis is needed to address current technological requirements.
There is a need for an efficient and accurate measuring system for estimating the coupled noise for on-chip interconnects. Additionally, there is a need for a system which can analyze noise for all circuit topologies within an acceptable time frame.